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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 preliminary information rev. 00f 11/14/05 IS34C02 issi ? copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. 2k-bit 2-wire serial cmos eeprom with permanent write-protection features ? two-wire serial interface, i 2 c tm compatible ? bidirectional data transfer protocol ? 400 khz (2.5v) and 1 mhz (5.0v) compatibility ? wide voltage operation ? vcc = 1.8v to 5.5v ? organization: ? 256 x 8-bit ? data protection features ? write protect pin ? permanent software protection ? 16-byte page write buffer ? partial page-writes permitted ? low power cmos technology ? active current less than 2 ma (5v) ? standby current less than 6 a (5v) ? standby current less than 2 a (2.5v) ? random or sequential read modes ? filtered inputs for noise suppression ? self timed write cycle with auto clear ? 5 ms max. @ 2.5v ? high reliability ? endurance: 1,000,000 cycles ? data retention: 40 years ? automotive and industrial temperature ranges ? 8-pin soic, 8-pin tssop, and 8-pin msop ? lead-free available preliminary information november 2005 description the IS34C02 is an electrically erasable prom device that uses the standard 2-wire interface for communications. the IS34C02 contains a memory array of 2,048-bits (256 x 8), and is further subdivided into 16 pages of 16 bytes each for page-write mode. the software write-protection feature is initiated with a unique irreversible instruction. after this command is transmitted, the first 128 bytes of the array become permanently read-only. this feature is popular in applications like dram dimms to retain dram related data. this eeprom operates in a wide voltage range of 1.8v to 5.5v to be compatible with most application voltages. issi designed the IS34C02 as a low-cost and low-power 2-wire eeprom solution. the devices are packaged in 8-pin soic, and 8-pin tssop, and 8-pin msop. the IS34C02 maintains compatibility with the popular 2- wire bus protocol, so it is easy to use in applications implementing this bus type. the simple bus consists of the serial clock wire (scl) and the serial data wire (sda). using the bus, a master device such as a microcontroller is usually connected to one or more slave devices such as the IS34C02. the bit stream over the sda line includes a series of bytes, which identifies a particular slave device, an instruction, an address within that slave device, and a series of data, if appropriate. the IS34C02 has a write protect pin (wp) to allow blocking of any write instruction transmitted over the bus.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? functional block diagram > control logic x decoder slave address register & comparator word address counter high voltage generator, timing & control y decoder data register clock di/o ack gnd wp scl sda vcc nmos a0 a1 a2 array 80h-ffh 00h-7fh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 preliminary information rev. 00f 11/14/05 IS34C02 issi ? pin descriptions a0-a2 address inputs sda serial address/data i/o scl serial clock input wp write protect input vcc power supply gnd ground scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi-directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wire or'ed with other open drain or open collector outputs. the sda bus requires a pullup resistor to vcc. pin configuration 8-pin soic, tssop, msop wp wp is the write protect pin. if the wp pin is tied to vcc, the entire array becomes write protected, and software write- protection cannot be initiated. when wp is tied to gnd or left floating, normal read/write operations are allowed to the device. if the device has already received a write-protection command, the memory in the range of 00h-7fh is read -only regardless of the setting of the wp pin. 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda a0, a1, a2 the a0, a1, and a2 are the device address inputs that are hardwired or left unconnected for hardware flexibility. when pins are hardwired, as many as eight devices may be addressed on a single bus system. when the pins are not hardwired, the default values of a0, a1, and a2 are zero. device operation the IS34C02 features a serial communication and supports a bi-directional 2-wire bus transmission protocol called i 2 c tm . 2-wire bus the two-wire bus is defined as a serial data line (sda), and a serial clock line (scl). the protocol defines any device that sends data onto the sda bus as a transmitter, and the receiving device as a receiver. the bus is controlled by master device which generates the scl, controls the bus access and generates the stop and start conditions. the IS34C02 is the slave device on the bus.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? the bus protocol: ? data transfer may be initiated only when the bus is not busy ? during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda line represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. start condition the start condition precedes all commands to the device and is defined as a high to low transition of sda when scl is high. the IS34C02 monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defined as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge (ack) after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the IS34C02 contains a reset function in case the 2- wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. the reset is caused when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode power consumption is reduced in standby mode. the IS34C02 will enter standby mode: a) at power-up, and remain in it until scl or sda toggles; b) following the stop signal if no write operation is initiated; or c) following any internal write operation device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave devices it is requesting. the slave device (fig. 5) address is 8 bits. the four most significant bits of the slave device address are fixed as 1010 for normal read/write operations, and 0110 for permanent write-protection operations. this device has three address bits (a1, a2, and a0) that allow up to eight IS34C02 devices to share the 2-wire bus. upon receiving the slave address, the device compares the three address bits with the hardwired a2, a1, and a0 input pins to determine if it is the appropriate slave. if any of the a2 - a0 pins is neither biased to high nor low, internal circuitry defaults the value to low. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master transmits the start condition and slave address byte (fig. 5), the appropriate 2-wire slave (eg. IS34C02) will respond with ack on the sda line. the slave will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the selected IS34C02 then prepares for a read or write operation by monitoring the bus.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 preliminary information rev. 00f 11/14/05 IS34C02 issi ? write operation byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w set to zero) to the slave device. after the slave generates an ack, the master sends a byte address that is written into the address pointer of the IS34C02. after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the IS34C02 acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the IS34C02 is capable of 16-byte page-write operation. a page-write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data byte is transferred, the master device can transmit up to 15 more bytes. after the receipt of each dat a byte, the IS34C02 responds immediately with an ack on sda line, and the four l ower order data byte address bits are internally incremented by one, while the higher order bits of the data byte address remain constant. if a byte address is incremented from the last byte of a page, it returns to the first byte of that page. if the m aster device should transmit more than 16 bytes prior to issuing the stop condition, the address counter will ?roll over,? and the previously written data will be overwritten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the IS34C02 in a single write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the IS34C02 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the IS34C02 is still busy with the write operation, no ack will be returned. if the IS34C02 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. permanent write protection the IS34C02 contains a permanent write protection feature that is initiated by means of a software command. after the command is transmitted, the protected area becomes irreversibly read-only despite power removal and re- application on the device. the address range of the 128 bytes of the array that is affected by this feature is 00h-7fh. once enabled, the permanent protection is independent of the status of the wp pin. (if wp is raised to high, the entire array is read-only. if wp is low, the region 00h-7fh can still be read-only.) the software command is initiated similarly to a normal byte write operation; however, the slave address begins with the bits 0110 (see figure 5). the following three bits are a2 - a0. the last bit of the slave address (r/ w) is 0. if the IS34C02 responds with ack, the device has not yet had its write-protection permanently enabled. to complete the command, the master must transmit a dummy address byte, dummy data byte, and a stop signal (see figure 11). the wp pin must be low during this command. before resuming any other command, the internal write cycle should be observed. the status of the permanent write protection can be safely determined without any changes by transmitting the same slave address as above, but with the last bit (r/ w) set to 1 (see figure 12). if the permanent write protection has been enabled, the IS34C02 will not acknowledge any slave address starting with bits 0110 (see figure 5).
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? sequential read sequential reads can be initiated as either a current address read or random address read. after the IS34C02 sends the initial byte sequence, the master device responds with an ack indicating it requires additional data from the IS34C02. the IS34C02 continues to output data for each ack received. the master device terminates the sequential read operation by pulling sda high (no ack) indicating the last data byte to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1, ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operations. when the memory address boundary 255 is reached, the address counter ?rolls over? to address 0, and the IS34C02 continues to output data for each ack received. (refer to figure 10. sequential read operation starting with a random address read diagram.) read operation read operations are initiated in the same manner as write operations, except that the (r/ w ) bit of the slave address is set to ?1?. there are three read operation options: current address read, random address read and sequential read. current address read the IS34C02 contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the IS34C02 receives the device addressing byte with a read operation (r/ w bit set to ?1?), it will respond an ack and transmit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the IS34C02 discontinues transmission. if the last byte of the memory was the previous access, the data from location '0' will be transmitted. (refer to figure 8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a 'dummy' write operation by sending the start condition, slave address and word address of the location it wishes to read. after the IS34C02 acknowledges the word address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the IS34C02 then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 preliminary information rev. 00f 11/14/05 IS34C02 issi ? scl sda master transmitter/ receiver IS34C02 vcc figure 1. typical system bus configuration t aa data output from transmitter scl from master data output from receiver 189 ack t a a figure 2. output acknowledge stop condition scl sda start condition figure 3. start and stop conditions
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? figure 5. slave address figure 4. data validity protocol scl sda data stable data stable data change 7 bit 43 1 2 5 60 r/ w a0 a1 a2 0 1 0 1 normal instruction 7 bit 43 1 2 5 60 r/ w a0 a1 a2 0 1 01 permanent write protect instruction figure 6. byte write figure 7. page write sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/ w a c k a c k a c k data device address word address *** * acknowledges provided by the slave regardless of hardware or software write protection. sda bus activity s t a r t m s b l s b w r i t e a c k a c k a c k a c k data (n+1) data (n) word address (n) device address s t o p a c k data (n+15) r/w ** * * * * acknowledges provided by the slave regardless of hardware or software write protection.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 preliminary information rev. 00f 11/14/05 IS34C02 issi ? figure 8. current address read figure 9. random address read sda bus activity s t a r t m s b l s b n o a c k r e a d s t o p a c k data device address r/w sda bus activity a c k a c k a c k data n word address (n) device address dummy write device address s t a r t w r i t e r e a d s t a r t s t o p m s b l s b n o a c k r/w figure 10. sequential read s t o p n o a c k a c k a c k a c k a c k data byte n+x data byte n+1 data byte n data byte n+2 r/w sda bus activity device address r e a d
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? figure 11. permanent write protection initiation figure 12. permanent write protection verification sda bus activity s t a r t m s b l s b r e a d a c k device address r/w s t o p * * the slave does not provide an acknowledgement if the permanent write protection is already enabled. sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/w a c k a c k a c k data device address word address * * the slave does not provide an acknowledgement if the permanent write protection is already enabled. # ### ## ## ######## # don't care bits are required.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 preliminary information rev. 00f 11/14/05 IS34C02 issi ? absolute maximum ratings (1) symbol parameter value unit v s supply voltage ?0.5 to +6.5 v v p voltage on any pin ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (IS34C02-2) range ambient temperature v cc industrial ?40c to +85c 1.8v to 5.5v note: issi offers industrial grade for commercial applications (0 o c to +70 o c) operating range (IS34C02-3) range ambient temperature v cc automotive ?40c to +125c 2.5v to 5.5v capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 5.0v.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? dc electrical characteristics industrial (t a = -40 o c to +85 o c), automotive (t a = -40 o c to +125 o c) symbol parameter test conditions min. max. unit v ol 1 output low voltage v cc = 1.8v, i ol = 0.15 ma ? 0.2 v v ol 2 output low voltage v cc = 2.5v, i ol = 3 ma ? 0.4 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?1.0 v cc x 0.3 v i li input leakage current v in = v cc max. ? 3 a i lo output leakage current ? 3 a ac electrical characteristics industrial (t a = -40 o c to +85 o c) 1.8v vcc < 2.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v (1) symbol parameter min. m ax. min. max. min. max. unit f scl scl clock frequency 0 100 0 400 0 1000 khz t noise suppression time (1) ? 100 ? 50 ? 50 ns t low clock low period 4.7 ? 1.2 ? 0.6 ? s t high clock high period 4 ? 0.6 ? 0.4 ? s t buf bus free time before new transmission (1) 4.7 ? 1.2 ? 0.5 ? s t su:sta start condition setup time 4 ? 0.6 ? 0.25 ? s t su:sto stop condition setup time 4 ? 0.6 ? 0.25 ? s t hd:sta start condition hold time 4 ? 0.6 ? 0.25 ? s t hd:sto stop condition hold time 4 ? 0.6 ? 0.25 ? s t su:dat data in setup time 100 ? 100 ? 100 ? ns t hd:dat data in hold time 0 ? 0 ? 0 ? ns t su : wp wp pin setup time 4 ? 0.6 ? 0.6 ? s t hd : wp wp pin hold time 4.7 ? 1.2 ? 1.2 ? s t dh data out hold time 100 ? 50 ? 50 ? ns (scl low to sda data out change) t aa clock to output 100 3500 50 900 50 400 ns (scl low to sda data out valid) t r scl and sda rise time (1) ? 1000 ? 300 ? 300 ns t f scl and sda fall time (1) ? 300 ? 300 ? 100 ns t wr write cycle time ? 10 ? 5 ? 5 ms power supply characteristics industrial (t a = -40 o c to +85 o c), automotive (t a = -40 o c to +125 o c) symbol parameter test conditions min. max. unit i cc 1 vcc operating current read at 400 khz (vcc = 5v) ? 2.0 ma i cc 2 vcc operating current write at 400 khz (vcc = 5v) ? 3.0 ma i sb 1 standby current vcc = 1.8v ? 1 a i sb 2 standby current vcc = 2.5v ? 2 a i sb 3 standby current vcc = 5.0v ? 6 a notes: v il min and v ih max are reference only and are not tested. note: 1. these parameters are characterized, but not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 preliminary information rev. 00f 11/14/05 IS34C02 issi ? ac electrical characteristics automotive (t a = -40 o c to +125 o c) 2.5v vcc < 4.5v 4.5v vcc 5.5v (1) symbol parameter min. max. min. max. unit f scl scl clock frequency 0 400 0 1000 khz t noise suppression time (1) ?50 ? 50 ns t low clock low period 1.2 ? 0.6 ? s t high clock high period 0.6 ? 0.4 ? s t buf bus free time before new transmission (1) 1.2 ? 0.5 ? s t su:sta start condition setup time 0.6 ? 0.25 ? s t su:sto stop condition setup time 0.6 ? 0.25 ? s t hd:sta start condition hold time 0.6 ? 0.25 ? s t hd:sto stop condition hold time 0.6 ? 0.25 ? s t su:dat data in setup time 100 ? 100 ? ns t hd:dat data in hold time 0 ? 0 ? ns t su : wp wp pin setup time 0.6 ? 0.6 ? s t hd : wp wp pin hold time 1.2 ? 1.2 ? s t dh data out hold time (scl low to sda data out change) 50 ? 50 ? ns t aa clock to output (scl low to sda data out valid) 50 900 50 550 ns t r scl and sda rise time (1) ? 300 ? 300 ns t f scl and sda fall time (1) ? 300 ? 100 ns t wr write cycle time ? 10 ? 5 ms note: 1. these parameters are characterized but not 100% tested.
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00f 11/14/05 IS34C02 issi ? 8th bit ack word n stop condition start condition t wr scl sda figure 14. write cycle timing figure 13. ac waveforms t su:sta t f t high t low t r t su:sto t buf t dh t aa t hd:sta t hd:dat t su:dat scl sda in sda out t su:wp t hd:wp wp
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 preliminary information rev. 00f 11/14/05 IS34C02 issi ? ordering information industrial range: -40c to +85c, lead-free voltage range part number package 1.8v IS34C02-2gli small outline (jedec std) (8-pin) to 5.5v IS34C02-2sli msop IS34C02-2zli tssop industrial range: ?40c to +85c voltage range part number package 1.8v IS34C02-2gi small outline (jedec std) (8-pin) to 5.5v IS34C02-2si msop IS34C02-2zi tssop
integrated silicon solution, inc. ? 1-800-379-4774 packaging information issi ? issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2002, integrated silicon solution, inc. plastic msop package code: s notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic msop (s) ref. std. jedec mo 187 no. leads 8 (120 mil) inches m illimeters symbol min max min max a 0.038 0.043 0.97 1.10 a1 0.002 0.006 0.05 0.15 b 0.010 0.016 0.25 0.40 c 0.005 0.009 0.13 0.23 d 0.114 0.122 2.90 3.10 e 0.193 bsc 4.90 bsc e1 0.114 0.122 2.90 3.10 e 0.0256 bsc 0.65 bsc l ? 0.022 ? 0.55 ?7 ?7 rev. d 02/01/02 d seating plane b e c 1 n e1 a1 a e l
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 2 rev. c 10/03/01 150-mil plastic sop package code: g, gr d seating plane b e c 1 n e a1 a h l notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 150-mil plastic sop (g, gr) symbol min max min max ref. std. inches mm no. leads 8 8 a ? 0.068 ? 1.73 a1 0.004 0.009 0.1 0.23 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.18 0.25 d 0.189 0.197 4.8 5 e 0.150 0.157 3.81 3.99 h 0.228 0.245 5.79 6.22 e 0.050 bsc 1.27 bsc l 0.020 0.035 0.51 0.89
integrated silicon solution, inc. packaging information issi ? thin shrink small outline tssop package code: z (8 pin, 14 pin) rev b 02/01/02 tssop (z) ref. std. jedec mo-153 no. leads 8 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e1 4.30 4.50 0.169 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 ?8 ?8 tssop (z) ref. std. jedec mo-153 no. leads 14 millimeters i nches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e1 4.30 4.50 0.170 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.0177 0.0295 ?8 ? 8 d b e e1 a2 e c a a1 l 1 n n/2 ssi reserves the right to make changes to its products at any time without notice in order to improve design and supply the bes t possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2002, integrated silicon solution, inc.

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